74LS161 4-bit synchronous binary counter

Description

The 74LS161 is a 4-bit synchronous binary counter belonging to the LS (Low-power Schottky) TTL family.
It counts in binary from 0 to 15 and all flip-flops are clocked simultaneously (synchronous operation).
The counter supports synchronous parallel loading, count enable, and asynchronous clear.

It is widely used in digital counters, frequency division, timing circuits, and control applications.

Key Features

• 4-bit synchronous binary counter

• Synchronous parallel load

• Asynchronous clear (reset)

• Two count enable inputs (ENP and ENT)

• Ripple carry output (RCO) for cascading counters

• Operates on TTL logic levels

• Faster and lower power than standard TTL counters

Pin Functions (Important Pins)

• CLK – Clock input (positive edge triggered)

• CLR – Asynchronous clear (active LOW)

• LOAD – Parallel load control (active LOW)

• ENP, ENT – Count enable inputs

• A, B, C, D – Parallel data inputs

• QA, QB, QC, QD – Counter outputs

• RCO – Ripple carry output

Working Principle

• When CLR = 0, the counter resets to 0000

• When LOAD = 0, data from A–D is loaded into the counter

• When ENP = ENT = 1, the counter increments on every clock pulse

• RCO goes HIGH when the counter reaches 1111, enabling cascading