SN74LS165AN SN74LS165N 74LS165 DIP-16 Parallel Load 8-Bit Shift Register IC

The 74LS165 is a 8-bit serial shift register that shifts the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD\ high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD\ is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs.

Features:

• Complementary outputs
• Direct overriding (data) inputs
• Gated clock inputs
• Parallel-to-serial data conversion
• Typical frequency 35 MHz
• Typical power dissipation 105 mW

Note:

16 pin DIP. Actual brand may vary from picture.

Technical Specifications:

Datasheet:

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