CD4073 CMOS Triple 3-Input AND Gate Breadboard-Friendly IC DIP-14

Features:

• Medium-Speed Operation – tPLH, tPHL= 60 ns (typ.) at VDD= 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range: 100nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  • 1 V at VDD= 5 V
  • 2 V at VDD= 10 V
  • 2.5 V at VDD= 15 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”